Circuit-Level Design and Simulation of a 10-bit Pipeline ADC (2016)
In this project, I conducted the systematic and circuit-level design and simulation of a 10-bit pipeline Analog-to-Digital Converter (ADC) using MATLAB and Cadence Virtuoso, adhering to defined specifications in 0.18 µm TSMC CMOS technology. The ADC was designed with a resolution of 10 bits, a signal bandwidth of 10 MHz, and a Nyquist rate of 35 MHz, achieving a Signal-to-Noise-and-Distortion Ratio (SNDR) greater than 58 dB at the maximum frequency. It maintained differential non-linearity (DNL) within ±0.5 LSB and integral non-linearity (INL) within ±1 LSB while operating over an input full-scale range of 2 Vpp. The design utilized a 1.8 V power supply and was evaluated under nominal, fast, and slow process corners to ensure robustness and compliance with the specifications.
