Transistor-Level Design and Simulation of a Viterbi Decoder (2015)
I designed and simulated a Viterbi encoder and decoder at the transistor level using 0.18 µm CMOS technology in Cadence Virtuoso. The Viterbi algorithm is a maximum-likelihood sequence detection algorithm widely used for decoding convolutionally encoded data in communication systems. It operates by identifying the most likely sequence of states in a trellis diagram, which represents all possible state transitions of the encoder. My design involved implementing the encoding process, which generates a sequence of parity bits from input data using convolutional logic, and the decoding process, which reconstructs the original data by tracing the optimal path through the trellis based on received signals. At the transistor level, the encoder and decoder were designed with a focus on efficient state representation, branch metric computation, and path metric accumulation. Simulations verified the accuracy of the encoding and decoding processes, as well as the design's performance, power efficiency, and reliability under various operating conditions.
